DS152 Datasheet, PDF (18/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
GTH Transceiver Switching Characteristics
Consult Virtex-6 FPGA GTH Transceivers User Guide for further information.
Table 32: GTH Transceiver Maximum Data Rate and PLL Frequency Range
Symbol
Description
Conditions
Speed Grade
-3
-2
-1
F_GTHMAX
Maximum GTH transceiver data rate
PLL Output Divider = 1
PLL Output Divider = 4
11.182
2.795
11.182
2.795
10.32
2.58
F_GTHMIN
PLL Output Divider = 1
9.92
9.92
9.92
Minimum GTH transceiver data rate⁽¹⁾
PLL Output Divider = 4
2.48
2.48
2.48
F_GPLLMAX
F_GPLLMIN
Maximum GTH PLL frequency
Minimum GTH PLL frequency
5.591
5.591
5.16
4.96
4.96
4.96
Notes:
1. Lower data rates can be achieved using FPGA logic based oversampling designs.
Table 33: GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
F_GTHDRPCLK GTHDRPCLK maximum frequency
70
70
60
Table 34: GTH Transceiver Reference Clock Switching Characteristics
Symbol
Description
Conditions
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_LOCK
T_PHASE
Reference clock frequency range
Reference clock rise time
Reference clock fall time
Reference clock duty cycle
Clock recovery frequency acquisition
time
Clock recovery phase acquisition time
-1 speed grade
-2 and -3 speed grades
20% – 80%
80% – 20%
CLK
Initial PLL lock
Lock to data after PLL has locked
to the reference clock
All Speed Grades
Min
Typ
Max
150
623
150
670
200
200
45
50
55
X-Ref Target - Figure 5
80%
T_RCLK
Units
Gb/s
Gb/s
Gb/s
Gb/s
GHz
GHz
Units
MHz
Units
MHz
MHz
ps
ps
%
ms
µs
20%
T_FCLK
ds152_05_042109
Figure 5: Reference Clock Timing Parameters
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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