DS152 Datasheet, PDF (47/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
MMCM Switching Characteristics
Table 63: MMCM Specification
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
F_INMAX
F_INMIN
F_INJITTER
F_INDUTY
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
800
750
700
700
MHz
10
10
10
10
MHz
< 20% of clock input period or 1 ns Max
25/75
%
30/70
%
Allowable Input Duty Cycle: 200—399 MHz
35/65
%
Allowable Input Duty Cycle: 400—499 MHz
40/60
%
Allowable Input Duty Cycle: >500 MHz
45/55
%
F_{MIN_PSCLK}
F_{MAX_PSCLK}
F_VCOMIN
F_VCOMAX
F_BANDWIDTH
T_{STATPHAOFFSET}
T_OUTJITTER
T_OUTDUTY
T_LOCKMAX
F_OUTMAX
F_OUTMIN
T_EXTFDVAR
RST_MINPULSE
F_PFDMAX
Minimum Dynamic Phase Shift Clock Frequency
Maximum Dynamic Phase Shift Clock Frequency
Minimum MMCM VCO Frequency
Maximum MMCM VCO Frequency
Low MMCM Bandwidth at Typical⁽¹⁾
High MMCM Bandwidth at Typical⁽¹⁾
Static Phase Offset of the MMCM Outputs⁽²⁾
MMCM Output Jitter⁽³⁾
MMCM Output Clock Duty Cycle Precision⁽⁴⁾
MMCM Maximum Lock Time
MMCM Maximum Output Frequency
MMCM Minimum Output Frequency⁽⁵⁾⁽⁶⁾
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to High or Optimized
0.01
0.01
0.01
0.01 MHz
550
500
450
450
MHz
600
600
600
600
MHz
1600
1440
1200
1200 MHz
1.00
1.00
1.00
1.00 MHz
4.00
4.00
4.00
4.00 MHz
0.12
0.12
0.12
0.12
ns
Note 1
0.15
0.20
0.20
0.20
ns
100
100
100
100
µs
800
750
700
700
MHz
4.69
4.69
4.69
4.69 MHz
< 20% of clock input period or 1 ns Max
1.5
1.5
1.5
1.5
ns
550
500
450
450
MHz
Maximum Frequency at the Phase Frequency
Detector with Bandwidth Set to Low
300
300
300
300
MHz
F_PFDMIN
Minimum Frequency at the Phase Frequency
Detector
10.00 10.00 10.00 10.00 MHz
T_FBDELAY
T_{MMCMDCK_PSEN}/
T_{MMCMCKD_PSEN}
T_{MMCMDCK_PSINCDEC}/
T_{MMCMCKD_PSINCDEC}
T_{MMCMCKO_PSDONE}
Maximum Delay in the Feedback Path
Setup and Hold of Phase Shift Enable
Setup and Hold of Phase Shift
Increment/Decrement
Phase Shift Clock-to-Out of PSDONE
3 ns Max or one CLKIN cycle
1.04
1.04
1.04
1.04
ns
0.00
0.00
0.00
0.00
1.04
1.04
1.04
1.04
ns
0.00
0.00
0.00
0.00
0.32
0.34
0.38
0.38
ns
Notes:
1. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. The static offset is measured between any MMCM outputs with identical phase.
3. Values for this parameter are available in the Architecture Wizard.
4. Includes global clock buffer.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
6. When CASCADE4_OUT = TRUE, F_OUTMIN is 0.036 MHz.
DS152 (v2.10) October18, 2010
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