DS152 Datasheet, PDF (55/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Table 72: Sample Window
Symbol
T_SAMP
T_{SAMP_BUFIO}
Description
Sampling Error at Receiver Pins⁽¹⁾
Sampling Error at Receiver Pins using
BUFIO⁽²⁾
Device
-3
All
510
All
300
Speed Grade
-2
-1
560
610
350
400
Units
-1L
670
ps
440
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the MMCM to capture the DDR input registers’ edges of operation. These measurements
include:
- CLK0 MMCM jitter
- MMCM accuracy (phase offset)
- MMCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-6 FPGA DDR input registers, measured across voltage, temperature, and
process. The characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of
operation. These measurements do not include package or clock tree skew.
Table 73: Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
-3
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T_PSCS/T_PHCS
Setup/Hold of I/O clock
–0.28
1.09
Pin-to-Pin Clock-to-Out Using BUFIO
T_ICKOFCS
Clock-to-Out of I/O clock
4.22
Speed Grade
-2
-1
–0.28 –0.28
1.16 1.33
4.59 5.22
Units
-1L
–0.18 ns
1.79
5.63
ns
Revision History
The following table shows the revision history for this document:
Date
06/24/09
07/16/09
08/19/09
09/16/09
Version
1.0
1.1
1.2
2.0
Description of Revisions
Initial Xilinx release.
Revised the maximum V_CCAUX and V_IN numbers in Table 2, page 2. Removed empty column from
Table 3, page 2. Revised specifications on Table 20, page 11. Updated Table 38, page 20 and added
notes 1 and 2. Revised T_{DLYCCO_RDY}, T_{IDELAYCTRL_RPW}, and T_{IDELAYPAT_JIT} in Table 52, page 35.
Updated Table 57, page 40 to more closely match the DSP48E1 speed specifications. Updated
T_TAPTCK/T_TCKTAP in Table 58, page 43. Updated XC6VLX130T parameters in Table 67 through
Table 69, page 52.
Added values for -1L voltages and speed grade in all pertinent tables. Added V_FS and notes to Table 1
and Table 2. Removed DV_PPIN from the example in Figure 2. Added networking applications to
Table 41, page 23. Changed and added to the block RAM F_MAX section in Table 56, page 39 including
removing Note 12. Changed F_PFDMAX values and corrected units for T_{STATPHAOFFSET} and T_OUTDUTY
in Table 63, page 47. Updated Table 70, page 53.
Added Virtex-6 HXT devices to entire document including GTH Transceiver Specifications. Updated
speed specifications as described in Switching Characteristics, includes changes in Table 50,
Table 56, Table 57, and Table 65 through Table 69. Comprehensive changes to Table 14, Table 15, and
Table 16. Added conditions to D_VPPOUT and revised description of T_OSKEW in Table 17. Removed V_ISE
specification and note from Table 18. Added note 3 to Table 23. Updated note 3 in Table 24. Updated
LVCMOS25 delays in Table 44. Updated specification for T_IOTPHZ in Table 45. Removed T_BUFHSKEW
from Table 70, page 53 and added values for T_BUFIOSKEW. Added values in Table 73.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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