DS152 Datasheet, PDF (46/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 59: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
T_{BCCCK_CE}/T_{BCCKC_CE(1)}
T_{BCCCK_S}/T_{BCCKC_S(1)}
T_{BCCKO_O(2)}
Maximum Frequency
Description
CE pins Setup/Hold
S pins Setup/Hold
BUFGCTRL delay from I0/I1 to O
-3
0.11/
0.00
0.11/
0.00
0.07
Speed Grade
-2
-1
0.13/
0.00
0.16/
0.00
0.13/
0.00
0.16/
0.00
0.08
0.10
-1L
0.13/
0.00
0.13/
0.00
0.10
Units
ns
ns
ns
F_MAX
Global clock tree (BUFG)
800
750
700
667
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. T_{BGCKO_O} (BUFG delay from I0 to O) values are the same as T_{BCCKO_O} values.
Table 60: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
T_{BIOCKO_O}
Maximum Frequency
F_MAX
Clock to out delay from I to O
I/O clock tree (BUFIO)
Speed Grade
Units
-3
-2
-1
-1L
0.14
0.16
0.18
0.21
ns
800
800
710
710
MHz
Table 61: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
T_{BRCKO_O}
Clock to out delay from
I to O
T_{BRCKO_O_BYP}
Clock to out delay from I to O with Divide Bypass
attribute set
T_{BRDO_O}
Maximum Frequency
Propagation delay from CLR to O
F_MAX(1)
Regional clock tree (BUFR)
Notes:
1. The maximum input frequency to the BUFR is the BUFIO F_MAX frequency.
-3
0.56
0.28
0.69
500
Speed Grade
-2
-1
0.62
0.73
0.31
0.36
0.74
0.80
420
300
Units
-1L
0.82
ns
0.41
ns
1.12
ns
300
MHz
Table 62: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol
T_{BHCKO_O}
T_{BHCCK_CE}/T_{BHCKC_CE}
Maximum Frequency
F_MAX
Description
BUFH delay from I to O
CE pin Setup and Hold
Horizontal clock buffer (BUFH)
-3
0.10
0.04/
0.04
800
Speed Grade
-2
-1
0.11
0.13
0.04/
0.04
0.05/
0.05
750
700
-1L
0.15
0.04/
0.04
Units
ns
ns
667
MHz
DS152 (v2.10) October18, 2010
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Advance Product Specification
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