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DS152 Datasheet, PDF (53/56 Pages) Xilinx, Inc – DC and Switching Characteristics
Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Clock Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-6 FPGA clock
transmitter and receiver data-valid windows.
Table 70: Duty Cycle Distortion and Clock-Tree Skew
Symbol
Description
Device
TDCD_CLK
TCKSKEW
TDCD_BUFIO
TBUFIOSKEW
TBUFIOSKEW2
TDCD_BUFR
Global Clock Tree Duty Cycle
Distortion(1)
Global Clock Tree Skew(2)
All
XC6VLX75T
XC6VLX130T
XC6VLX195T
XC6VLX240T
XC6VLX365T
XC6VLX550T
XC6VLX760
XC6VSX315T
XC6VSX475T
XC6VHX250T
XC6VHX255T
XC6VHX380T
XC6VHX565T
I/O clock tree duty cycle distortion
All
I/O clock tree skew across one clock
All
region
I/O clock tree skew across three clock
All
regions
Regional clock tree duty cycle
All
distortion
Speed Grade
Units
-3
-2
-1
-1L
0.12
0.12
0.12
0.12
ns
0.15
0.16
0.18
0.17
ns
0.25
0.26
0.29
0.28
ns
0.26
0.27
0.31
0.30
ns
0.26
0.27
0.31
0.30
ns
0.28
0.29
0.31
0.31
ns
N/A
0.50
0.54
0.54
ns
N/A
0.51
0.56
0.56
ns
0.27
0.28
0.32
0.30
ns
N/A
0.39
0.44
0.42
ns
0.25
0.26
0.29
N/A
ns
0.35
0.37
0.41
N/A
ns
0.45
0.47
0.52
N/A
ns
N/A
0.46
0.51
N/A
ns
0.08
0.08
0.08
0.08
ns
0.03
0.03
0.03
0.02
ns
0.10
0.12
0.23
0.12
ns
0.15
0.15
0.15
0.15
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The TCKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
53