DS152 Datasheet, PDF (38/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
CLB Shift Register Switching Characteristics (SLICEM Only)
Table 55: CLB Shift Register Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Sequential Delays
T_REG
Clock to A – D outputs
T_{REG_MUX}
Clock to AMUX – DMUX output
T_{REG_M31}
Clock to DMUX output via M31 output
Setup and Hold Times Before/After Clock CLK
1.11
1.30
1.58
1.74
ns, Max
1.37
1.60
1.93
2.12
ns, Max
1.08
1.27
1.55
1.74
ns, Max
T_WS/T_WH
WE input
0.05/
0.00
0.07/
0.00
0.09/
0.00
0.11/
0.03
ns, Min
T_CECK/T_CKCE
CE input to CLK
0.06/
–0.01
0.08/
–0.01
0.10/
–0.01
0.12/
0.02
ns, Min
T_DS/T_DH
A – D inputs to CLK
0.64/
0.18
0.76/
0.21
0.94/
0.24
1.07/
0.23
ns, Min
Clock CLK
T_MPW
Minimum pulse width
0.60
0.70
0.85
0.89
ns, Min
Notes:
1. A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case”, but if a “0” is
listed, there is no positive hold time.
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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