DS152 Datasheet, PDF (33/56 Pages) Xilinx, Inc – DC and Switching Characteristics

Virtex-6 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 50: ISERDES Switching Characteristics
Symbol
Description
Setup/Hold for Control Lines
T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP} BITSLIP pin Setup/Hold with respect to CLKDIV
T_{ISCCK_CE} / T_{ISCKC_CE(2)}
CE pin Setup/Hold with respect to CLK (for CE1)
T_{ISCCK_CE2} / T_{ISCKC_CE2(2)}
Setup/Hold for Data Lines
T_{ISDCK_D} /T_{ISCKD_D}
CE pin Setup/Hold with respect to CLKDIV (for
CE2)
D pin Setup/Hold with respect to CLK
T_{ISDCK_DDLY} /T_{ISCKD_DDLY}
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)⁽¹⁾
T_{ISDCK_D_DDR} /T_{ISCKD_D_DDR} D pin Setup/Hold with respect to CLK at DDR
mode
T_{ISDCK_DDLY_DDR}
T_{ISCKD_DDLY_DDR}
Sequential Delays
D pin Setup/Hold with respect to CLK at DDR
mode (using IODELAY)⁽¹⁾
T_{ISCKO_Q}
Propagation Delays
CLKDIV to out at Q pin
T_{ISDO_DO}
D input to DO output pin
Notes:
1. Recorded at 0 tap value.
2. T_{ISCCK_CE2} and T_{ISCKC_CE2} are reported as T_{ISCCK_CE}/T_{ISCKC_CE} in TRACE report.
-3
0.07/
0.15
0.20/
0.03
0.01/
0.27
0.07/
0.08
0.10/
0.05
0.07/
0.08
0.10/
0.05
0.57
0.19
Speed Grade
-2
-1
Units
-1L
0.08/
0.16
0.25/
0.04
0.01
0.29
0.09/ 0.14/ ns
0.17
0.17
0.27/ 0.31/ ns
0.04
0.05
0.01/ –0.05/ ns
0.31
0.35
0.08/ 0.09/ 0.11/ ns
0.09
0.11
0.19
0.12/ 0.14/ 0.16/ ns
0.06
0.07
0.15
0.08/ 0.09/ 0.11/ ns
0.09
0.11
0.19
0.12/ 0.14/ 0.16/ ns
0.06
0.07
0.15
0.66
0.75
0.88
ns
0.22
0.25
0.28
ns
DS152 (v2.10) October18, 2010
www.xilinx.com
Advance Product Specification
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