TH58NVG5S0FTA20 Datasheet, PDF (7/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

AC TEST CONDITIONS
PARAMETER
Input level
Input pulse rise and fall time
Input comparison level
Output data comparison level
Output load
TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
CONDITION
V_CC: 2.7 to 3.6V
0V to Vcc
3 ns
Vcc / 2
Vcc / 2
C_L (100 pF) + 1 TTL
Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY pin.
(Refer to Application Note (9) toward the end of this document.)
PROGRAMMING AND ERASING CHARACTERISTICS
(Ta = 0 to 70ˆ, V_CC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
TYP.
t_PROG
Average Programming Time
⎯
300
t_DCBSYW1
Data Cache Busy Time in Write Cache (following 11h)
⎯
0.5
t_DCBSYW2
Data Cache Busy Time in Write Cache (following 15h)
⎯
⎯
N
Number of Partial Program Cycles in the Same Page
⎯
⎯
t_BERASE
Block Erasing Time
⎯
3
(1) Refer to Application Note (12) toward the end of this document.
(2) t_DCBSYW2 depends on the timing between internal programming time and data in time.
MAX
UNIT NOTES
700
µs
1
µs
700
µs
(2)
4
(1)
10
ms
Data Output
When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depend on tRHOH
(25ns MIN). On this condition, waveforms look like normal serial read mode.
When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depend on
tRLOH (5ns MIN). On this condition, output buffers are disabled by the rising edge of CLE,ALE,/CE or falling
edge of /WE, and waveforms look like Extended Data Output Mode.
7
2010-12-13C