TH58NVG5S0FTA20 Datasheet, PDF (36/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
(2) Multi Page Read with Data Cache
When the block address changes (increments) this sequenced has to be started from the beginning.
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command

input
60
Address input
60
Address input
30
A
Page Address
Page Address
PA0 to PA18
PA0 to PA18
(Page m0 ; District 0)
(Page n0 ; District 1)
tR
RY/BY
A
A
RY/BY _A
Command

input
31
00
Address input
05
tDCBSYR1
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page m0 ; District 0)
Address input
E0
Column Address
CA0 to CA12
(District 0)
Data output
B
(District 0)
B
B
RY/BY _B
Command

input
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page n0 ; District 1)
Address input
E0
Column Address
CA0 to CA12
(District 1)
Data output
C
(District 1)
C
Command

input
Return to A
Repeat a max of 63 times
C
3F
00
Address input
05
Address input
E0
Data output
D
RY/BY _C
tDCBSYR1
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page m63 ; District 0)
Column Address
CA0 to CA12
(District 0)
(District 0)
D
D
RY/BY _D
Command

input
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(Page n63 ; District 1)
Address input
E0
Column Address
CA0 to CA12
(District 1)
Data output
(District 1)
36
2010-12-13C