TH58NVG5S0FTA20 Datasheet, PDF (12/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

Read Cycle with Data Cache Timing Diagram (1/2)
TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
CLE
CE
t_CLS ^tCLH
t_CH
t_CS
t_WC
WE
t_ALH t_ALS
t_CLS ^tCLH
t_CH
t_CS
t_CLR
t_CLS ^tCLH
t_CH
t_CS
t_ALH t_ALS
t_RW
tCEA
t_CLR
t_CLS ^tCLH
t_CH
t_CS
tCEA
ALE
RE
I/O
RY / BY
t_DS t_DH
00h
t_DS t_DH t_DS t_DH t_DS t_DH t_DS t_DH t_DS t_DH
CA0 CA8
to 7 to 12
Column address
N*
PA0
PA8 PA16
to 7 to 15 to 18
Page address
M
t_R
t_WB
t_DS t_DH
30h
t_DCBSYR1
t_RC
t_DCBSYR1
t_WB
t_DS t_DH
31h
t_{RR tREA}
D_OUT D_OUT
0
1
t_WB
t_DS t_DH
D_OUT
31h
Page address M
Col. Add. 0
t_{RR tREA}
D_OUT
0
Page address
M+1
Col. Add. 0
* The column address will be reset to 0 by the 31h command input.
1
Continues to 1 of next page
12
2010-12-13C