TH58NVG5S0FTA20 Datasheet, PDF (46/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Command
6
input
A
8C
Address input
Data input
15
Address
When changing data,
CA0 to CA12, PA0 to PA18 _{changed data is input.}
(Page M+R1)
RY / BY A
00
Address input
3A
Address
CA0 to CA12, PA0 to PA18
(Page N+P2)
7
t_DCBSYW2
Data output
Col = 0 start
8
t_DCBSYR2
00
Address input
3A
Data output
B
Address
CA0 to CA12, PA0 to PA18
(Page N+Pn)
Col = 0 start
9
B
t_DCBSYR2
Data Cache
Page Buffer
Cell Array
6
Data for Page M + R1
Page M
Page N + P1
7
Data for Page M + R1
8 _{Data for Page N + P2}
Page M + R1
Page N + P2
Page M + Rn − 1
9 _{Data for Page N + Pn}
Page N + Pn
Page M + Rn − 1
6 Copy Page address (M + R1) is input and if the data needs to be changed, changed data is input.
7 After programming of page M is completed, Data Cache for Page M + R1 is transferred to the Page Buffer.
8 By the 15h command, the data in the Page Buffer is programmed to Page M + R1. Data for Page N + P2 is transferred to the Data cache.
9 The data in the Page Buffer is programmed to Page M + Rn − 1. Data for Page N + Pn is transferred to the Data Cache.
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2010-12-13C