TH58NVG5S0FTA20 Datasheet, PDF (56/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi Page Copy-Back using 4KB Buffer RAM
The deveice consists of 4KB pages and can support Multi Plane program operation. The internal RAM
requirement for a controller is 8KB, but for those controllers which support less than 8KB RAM, the sequence of
command, address and data input is shown below for Multi Plane program operation.
District0
Source page
Target page
(1)
(6)
District1
Source page
Target page
(1)
(6)
(1) : Two-Plane Read for Copy-Back
(2) : Random Data Out On Plane 0(Up to 4328Byte)
(3) : Random Data In On Plane 0(Up to 4328Byte)
(4) : Random Data Out On Plane 1(Up to 4328Byte)
(5) : Random Data In On Plane 1(Up to 4328Byte)
(6) : Two-Plane Program for Copy-Back
4KByte
Data field
Spare field
(2)
(3)
4KByte
Data field
Spare field
(4)
(5)
Multi Page Copy-Back with Random Data Input
tR
R/ B
I/Ox
R/ B
60h Add.(3Cycle) 60h Add.(3Cycle)
35h
Row Add.1,2,3
Row Add.1,2,3
PA0~PA5 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘Low’ PA6
: Fixed ‘High’
PA7~PA18 : Valid
PA7~PA18 : Valid
00h Add.(5Cycle) 05h Add.(2Cycle) E0h DOUT
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 Up to 4328Byte
CA0~CA12 : Fixed ‘Low’ CA0~CA12 : Valid
PA0~PA5 : Fixed ‘Low’
1
PA6
: Fixed ‘Low’
PA7~PA18 : Fixed ‘Low’
tDCBSYW1
I/Ox
R/ B
85h Add.(5Cycle) DIN 85h Add.(2Cycle) DIN
Col. Add.1,2 & Row Add.1,2,3
Destination Address
1
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘Low’
PA7~PA18 : Valid
Col. Add.1,2,
11h
00h Add.(5Cycle) 05h Add.(2Cycle) E0h DOUT
Col. Add.1,2 & Row Add.1,2,3 Col. Add.1,2 Up to 4328Byte
CA0~CA12 : Fixed ‘Low’ CA0~CA12 : Valid
PA0~PA5 : Fixed ‘Low’
2
PA6
: Fixed ‘High’
PA7~PA18 : Fixed ‘Low’
tPROG
I/Ox
81h Add.(5Cycle) DIN 85h Add.(2Cycle) DIN 10h
70h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
2
CA0~CA12 : Valid
PA0~PA5 : Valid
PA6
: Fixed ‘High’
PA7~PA18 : Valid
Col. Add.1,2,
NOTE: 1. Copy-Back is allowed only within the same memory district.
56
2010-12-13C