TH58NVG5S0FTA20 Datasheet, PDF (24/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi-Page Program Operation with Data Cache Timing Diagram (4/4)
t_CLS
CLE
t_CLS ^tCLH
t_CS
t_CS
CE
t_CH
WE
t_ALH
t_ALS
ALE
t_ALH
t_ALS
t_{PROG (*1)}
t_WB
RE
I/O
RY / BY
t_{DS tDH}
81h
t_DS t_DH
CA0 CA8 PA0 PA8 PA16
to 7 to 12 to 7 to 15 to 18
Page Address M+n
District-1
t_DS
t_DH
D_INN
D_IN
N+1
10h
D_IN4327
: Do not input data while data is being output.
: V_IH or V_IL
3
Continued from 3 of last page
t_DS
t_DH
71h
Status
(*1) t_PROG: Since the last page programming by 10h command is initiated after the previous cache
program, the t_PROG during cache programming is given by the following equation.
t_PROG = t_PROG of the last page + t_PROG of the previous page − A
A = (command input cycle + address input cycle + data input cycle time of the last page)
If “A” exceeds the t_PROG of previous page, t_PROG of the last page is t_PROG max.
(Note)
Make sure to terminate the operation with 80h-10h- command sequence.
If the operation is terminated by 81h-15h command sequence, monitor I/O 6 (Ready / Busy) by issuing Status
Read command (70h) and make sure the previous page program operation is completed. If the page program
operation is completed issue FFh reset before next operation.
24
2010-12-13C