TH58NVG5S0FTA20 Datasheet, PDF (29/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
PIN FUNCTIONS
The device is a serial access memory which utilizes time-sharing input of address information.
Command Latch Enable: CLE
The CLE input signal is used to control loading of the operation mode command into the internal command
register. The command is latched into the command register from the I/O port on the rising edge of the WE
signal while CLE is High.
Address Latch Enable: ALE
The ALE signal is used to control loading address information into the internal address register. Address
information is latched into the address register from the I/O port on the rising edge of WE while ALE is High.
Chip Enable: CE (n)
Since the device contains two 8Gbit chips, control for each chip by using CE 1 and CE 2. The chip not to be
selected is disabled while CE is High.
CE (n) signal is used to select the chip, and the chip goes into a low-power Standby mode when CE goes High
during the chip is in Ready state. The CE signal is ignored when device is in Busy state ( RY / BY = L), such
as during a Program or Erase or Read operation, and will not enter Standby mode even if the CE input goes
High.
Write Enable: WE
The WE signal is used to control the acquisition of data from the I/O port.
Read Enable: RE
The RE signal controls serial data output. Data is available t_REA after the falling edge of RE .
The internal column address counter is also incremented (Address = Address + l) on this falling edge.
I/O Port: I/O1 to 8
The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from
the device.
Write Protect: WP
The WP signal is used to protect the device from accidental programming or erasing. The internal voltage
regulator is reset when WP is Low. This signal is usually used for protecting the data during the power-on/off
sequence when input signals are invalid.
Ready/Busy: RY / BY (n)
The RY / BY output signal is used to indicate the operating condition of the device. The RY / BY signal is
in Busy state ( RY / BY = L) during the Program, Erase and Read operations and will return to Ready state
( RY / BY = H) after completion of the operation. The output buffer for this signal is an open drain and has to be
pulled-up to Vccq with an appropriate resister.
The device has RY / BY 1 and RY / BY 2 signal. RY / BY 1 indicates operating condition of the chip which
has CE 1, and RY / BY 2 indicates operating condition of the chip which has CE 2.
Power on Select: PSL
The PSL signal is used to select whether the device initialization should take place during the device power
on or during the first Reset. Please refer to the application note (2) for details.
29
2010-12-13C