TH58NVG5S0FTA20 Datasheet, PDF (30/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
[8Gbit ( Chip A,B)]
[8Gbit ( Chip C,D)]
Data Cache 4096
I/O1
232
I/O8
Data Cache 4096
I/O1
232
I/O8
Page Buffer 4096
232
Page Buffer 4096
232
524288
pages
8192
blocks
4328
64 Pages=1 block
524288
pages
8192
blocks
8I/O
64 Pages=1 block
8I/O
4328
A page consists of 4328 bytes in which 4096 bytes are used for main memory storage and 232 bytes are
for redundancy or for other uses.
1 page = 4328 bytes
1 block = 4328 bytes × 64 pages = (256K + 14.5K) bytes
Capacity = 4328 bytes × 64pages × 16384 blocks
Table 1. Addressing
First cycle
Second cycle
Third cycle
Fourth cycle
Fifth cycle
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0
L
L
L CA12 CA11 CA10 CA9 CA8
PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
CA0 to CA12: Column address
PA0 to PA18: Page address
PA6 to PA18: Block address
PA0 to PA5: NAND address in block
PA15 PA14 PA13 PA12 PA11 PA10 PA9 PA8
L
L
L
L
L PA18 PA17 PA16
30
2010-12-13C