TH58NVG5S0FTA20 Datasheet, PDF (54/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
2KB Program Operation Timing Guide
The device is designed also to support the program operation with 2KByte data to offer the backward
compatibility to the controller which uses the NAND Flash with 2KByte page. The sequence of command,
address and data input is shown below.
(2KBx2) Program Operation
tDCBSYW1
R/ B
tPROG
I/O0~7 80h Address & Data Input 11h
80h Address & Data Input 10h
70h
Note
Col. Add.1,2 & Row Add.1,2,3
2112 Byte Data
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Valid
: Valid
Col. Add.1,2 & Row Add.1,2,3
2112 Byte Data
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Must be same with the previous
: Must be same with the previous
: Must be same with the previous
NOTE: 1. Any command between 11h and 81h is prohibited except 70h/F1h and FFh
(2KBx2) Copy-Back
tR
R/ B
I/Ox
R/ B
00h Add.(5Cycles) 35h
Col. Add.1,2 & Row Add.1,2,3
Source Address
tDCBSYW1
Data Output
1
tPROG
I/Ox
85h Add.(5Cycles) Data 11h
1
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: Valid
: Valid
85h Add.(5Cycles) Data
10h
Col. Add.1,2 & Row Add.1,2,3
Destination Address
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Must be same with the previous
: Must be same with the previous
: Must be same with the previous
NOTE: 1. Copy-Back is allowed only within the same memory district.
2. Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
54
2010-12-13C