TH58NVG5S0FTA20 Datasheet, PDF (39/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi Page Program
The device has a Multi Page Program, which enables even higher speed program operation compared to Auto
Page Program. The sequence of command, address and data input is shown bellow. (Refer to the detailed timing
chart.)
Although two planes are programmed simultaneously, pass/fail is not available for each page when the program
operation completes. Status bit of I/O 1 is set to “1” when any of the pages fails. Limitation in addressing with
Multi Page Program is shown below.
Multi Page Program
tDCBSYW1
tPROG
R/ B
I/O0~7 80h Address & Data Input 11h
81h Address & Data Input 10h
70h
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid’
: District0’
: Valid’
Note
CA0~CA12
PA0~PA5
PA6
PA7~PA18
: Valid
: Valid
: District1
: Valid
”0”
I/O1
”1”
Fail
Pass
NOTE: Any command between 11h and 81h is prohibited except 70h/F1h and FFh.
80h
11h
81h
10h
Data
Input
Plane 0
(2048 Block)
Plane 1
(2048 Block)
Block 0
Block 2
Block 1
Block 3
Block 4092
Block 4094
Block 4093
Block 4095
39
2010-12-13C