TH58NVG5S0FTA20 Datasheet, PDF (23/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi-Page Program Operation with Data Cache Timing Diagram (3/4)
CLE
CE
t_CLS
t_CLS t_CLH
t_CS
t_CS
t_CH
WE
ALE
t_ALH
t_ALS
t_ALH
t_ALS
t_DCBSYW1
t_WB
RE
I/O
RY / BY
t_{DS tDH}
80h
t_DS t_DH
CA0 CA8 PA0 PA8 ^PA16
to 7 to 12 to 7 to 15 ^{to 18}
Page Address M+n
District-0
t_DS
t_DH
D_INN
D_IN
N+1
11h
D_IN4327
: Do not input data while data is being output.
: V_IH or V_IL
t_DS
t_DH
81h ^CA0
to 7
2
3
Continues to 3 of next page
23
2010-12-13C