TH58NVG5S0FTA20 Datasheet, PDF (22/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi-Page Program Operation with Data Cache Timing Diagram (2/4)
CLE
t_CLS
t_CLS t_CLH
t_CS
CE
t_CS
t_CH
WE
t_ALH
t_ALS
ALE
t_ALH
t_ALS
t_DCBSYW2
t_WB
RE
I/O
RY / BY
t_{DS tDH}
81h
t_DS t_DH
CA0 CA8 PA0 PA8 PA16
to 7 to 12 to 7 to 15 to 18
Page Address M
District-1
t_DS
t_DH
D_INN
D_IN
N+1
15h
D_IN4327
t_DS
t_DH
80h
CA0
to 7
Repeat a max of 63 times (in order to program pages 0 to 62 of a block).
1
2
Continued from 1 of last page
: Do not input data while data is being output.
: V_IH or V_IL
22
2010-12-13C