TH58NVG5S0FTA20 Datasheet, PDF (35/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi Page Read Operation
The device has a Multi Page Read operation and Multi Page Read with Data Cache operation..
(1) Multi Page Read without Data Cache
The sequence of command and address input is shown below.
Same page address (PA0 to PA5) within each district has to be selected.
Command

input
(3 cycle)
(3 cycle)
60
Address input
60
Address input
30
A
Page Address
Page Address
PA0 to PA18
PA0 to PA18
(District 0)
(District 1)
tR
RY/BY
A
RY/BY
Command

input
(5 cycle)
A
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(District 0)
A
(2 cycle)
Address input
E0
Column Address
CA0 to CA12
(District 0)
Data output
B
(District 0)
B
RY/BY
Command

input
(5 cycle)
B
00
Address input
05
Column + Page Address
CA0 to CA12, PA0 to PA18
(District 1)
B
Address input
E0
Column Address
CA0 to CA12
(District 1)
Data output
(District 1)
District 0
District 1
Selected
page
Reading
Selected
page
The data transfer operation from the cell array to the Data Cache via Page Buffer starts on the rising
edge of WE in the 30h command input cycle (after the 2 Districts address information has been
latched). The device will be in the Busy state during this transfer period.
After the transfer period, the device returns to Ready state. Serial data can be output synchronously
with the RE clock from the start address designated in the address input cycle.
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2010-12-13C