TH58NVG5S0FTA20 Datasheet, PDF (62/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL
APPLICATION NOTES AND COMMENTS
TH58NVG5S0FTA20
(1) Power-on/off sequence:
The timing sequence shown in the figure below is necessary for the power-on/off sequence.
The device internal initialization starts after the power supply reaches an appropriate level in the power on
sequence. During the initialization the device Ready/Busy signal indicates the Busy state as shown in the
figure below. In this time period, the acceptable commands are FFh or 70h/71h/F1h.
The WP signal is useful for protecting against data corruption at power-on/off.
0V
CE , WE , RE
CLE, ALE
WP
Ready/Busy
2.7 V
2.5 V
V_CC
Don’t
care
V_IL
100 µs max
V_IH
2 ms max
Operation
Invalid
2.7 V
2.5 V
≥ 1ms
0.5 V
0.5 V
Don’t
care
Don’t
care
V_IL
100 µs max
2 ms max
Don’t Invalid
care
(2) Power-on Reset
The device goes into automatic self-initialization during power on if PSL is tied either to GND or NU.
During the initialization process, the device consumes a maximum current of 30mA (ICCO0). If PSL is tied to
VCC, the device will not complete its self-initialization during power on and will not consume ICCO0, and
completes the initialization process with the first Reset command input after power on. During the first FFh
reset Busy period, the device consumes a maximum current of 30mA (ICCO0). In either case (PSL = GND/NU
or VCC), The following sequence is necessary because some input signals may not be stable at power-on.
Power on
FF
Reset
(3) Prohibition of unspecified commands
The operation commands are listed in Table 3. Input of a command other than those specified in Table 3 is
prohibited. Stored data may be corrupted if an unknown command is entered during the command cycle.
(4) Restriction of commands while in the Busy state
During the Busy state, do not input any command except 70h(71h, F1h,F2h) and FFh.
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2010-12-13C