TH58NVG5S0FTA20 Datasheet, PDF (31/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by command operations shown
in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE , WE ,
RE , WP and PSL signals, as shown in Table 2.
Table 2. Logic Table
CLE
ALE
CE
WE
RE
WP ^*1
PSL^*3
Command Input
H
L
L
H
*
0V/V_CC/NU
Data Input
L
L
L
H
H
0V/V_CC/NU
Address input
L
H
L
H
*
0V/V_CC/NU
Serial Data Output
L
L
L
H
*
0V/V_CC/NU
During Program (Busy)
*
*
*
*
*
H
0V/V_CC/NU
During Erase (Busy)
*
*
*
*
*
H
0V/V_CC/NU
During Read (Busy)
*
*
H
*
*
*
0V/V_CC/NU
*
*
L
H (*2)
H (*2)
*
0V/V_CC/NU
Program, Erase Inhibit
*
*
*
*
*
L
0V/V_CC/NU
Standby
*
*
H
*
*
0 V/V_CC 0V/V_CC/NU
H: V_IH, L: V_IL, *: V_IH or V_IL
*1: Refer to Application Note (10) toward the end of this document regarding the WP signal when Program or Erase Inhibit
*2: If CE is low during read busy, WE and RE must be held High to avoid unintended command/address input to the device or
read to device. Reset or Status Read command can be input during Read Busy.
*3: PSL must be tied to either 0V or V_CC or left unconnected(NU).
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2010-12-13C