TH58NVG5S0FTA20 Datasheet, PDF (6/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta = 0 to 70ˆ, V_CC = 2.7 to 3.6V)
SYMBOL
PARAMETER
MIN
t_CLS
CLE Setup Time
12
t_CLH
CLE Hold Time
5
t_CS
CE Setup Time
20
t_CH
CE Hold Time
5
t_WP
Write Pulse Width
12
t_ALS
ALE Setup Time
12
t_ALH
ALE Hold Time
5
t_DS
Data Setup Time
12
t_DH
Data Hold Time
5
t_WC
Write Cycle Time
25
t_WH
WE High Hold Time
10
t_WW
WP High to WE Low
100
t_RR
Ready to RE Falling Edge
20
t_RW
Ready to WE Falling Edge
20
t_RP
Read Pulse Width
12
t_RC
Read Cycle Time
25
t_REA
RE Access Time
⎯
tCEA
CE Access Time
⎯
t_CLR
CLE Low to RE Low
10
t_AR
ALE Low to RE Low
10
t_RHOH
RE High to Output Hold Time
25
t_RLOH
RE Low to Output Hold Time
5
t_RHZ
RE High to Output High Impedance
⎯
t_CHZ
CE High to Output High Impedance
⎯
t_CSD
CE High to ALE or CLE Don’t Care
0
t_REH
RE High Hold Time
10
t_IR
Output-High-impedance-to- RE Falling Edge
0
t_RHW
RE High to WE Low
60
t_WHC
WE High to CE Low
30
t_WHR
WE High to RE Low
60
t_R
Memory Cell Array to Starting Address
⎯
t_DCBSYR1
Data Cache Busy in Read Cache (following 31h and 3Fh)
⎯
MAX
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
20
25
⎯
⎯
⎯
⎯
60
20
⎯
⎯
⎯
⎯
⎯
⎯
30
30
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
t_DCBSYR2
Data Cache Busy in Page Copy (following 3Ah)
t_WB
WE High to Busy
t_RST
Device Reset Time (Ready/Read/Program/Erase)
*1: tCLS and tALS can not be shorter than tWP
*2: tCS should be longer than tWP + 8ns.
⎯
35
µs
⎯
100
ns
⎯
10/10/30/500
µs
6
2010-12-13C