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| TH58NVG5S0FTA20 Datasheet, PDF (61/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM | |||
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TOSHIBA CONFIDENTIAL
When a Reset (FFh) command is input during erasing
D0
FF
Internal erase
voltage
TH58NVG5S0FTA20
00
RY / BY
tRST (max 500 µs)
When a Reset (FFh) command is input during Read operation
00
30
FF
00
RY / BY
tRST (max 10 µs)
When a Reset (FFh) command is input during Ready
FF
00
RY / BY
tRST (max 10 µs)
When a Status Read command (70h) is input after a Reset
FF
70
RY / BY
When two or more Reset commands are input in succession
I/O status: Pass/Fail â Pass
: Ready/Busy â Ready
(1)
(2)
(3)
10
FF
FF
FF
RY / BY
The second FF command is invalid, but the third FF command is valid.
61
2010-12-13C
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