TH58NVG5S0FTA20 Datasheet, PDF (43/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation
total 64 times with incrementing the page address in the blocks, and then input the last page data of the
blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command
sequence.
In this full sequence, the command sequence is following.
1st 80
80
11
81
15
11
81
15
63th 80
64th 80
11
81
15
11
81
10
After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read
command.
10 or15
71
Status Read
command
Pass
I/O
Fail
RY/BY
The 71h command Status description is as below.
STATUS
OUTPUT
I/O1
Chip Status1 : Pass/Fail
Pass: 0
I/O2
District 0 Chip Status1 : Pass/Fail Pass: 0
I/O3
District 1 Chip Status1 : Pass/Fail Pass: 0
I/O4
District 0 Chip Status2 : Pass/Fail Pass: 0
I/O5
District 1 Chip Status2 : Pass/Fail Pass: 0
I/O6
Ready/Busy
Ready: 1
I/O7
Data Cache Ready/Busy
Ready: 1
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Fail: 1
Busy: 0
Busy: 0
I/O1 describes Pass/Fail condition of
district 0 and 1(OR data of I/O2 and I/O3).
If one of the districts fails during multi
page program operation, it shows “Fail”.
I/O2 to 5 shows the Pass/Fail condition of
each district. For details on “Chip Status1”
and “Chip Status2”, refer to section
“Status Read”.
I/O8
Write Protect
Protect: 0
Not Protect: 1
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2010-12-13C