TH58NVG5S0FTA20 Datasheet, PDF (42/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Multi Page Program with Data Cache
The device has a Multi Page Program with Data Cache operation, which enables even higher speed program
operation compared to Auto Page Program with Data Cache as shown below. When the block address changes
(increments) this sequenced has to be started from the beginning.
The sequence of command, address and data input is shown below. (Refer to the detailed timing chart.)
Data input
command
Data input
Dummy ^command
Program ^{for multi-page}
command ^program
Program with
Data Cache ^{Data input}
command ^command
Dummy
Program
command
Data input
command
for multi-page
program
Auto Page
Program
command
80
11
81
15
80
11
81
10
Address Data input
input 0 to 4327
(District 0)
Address Data input
input 0 to 4327
(District 1)
Address Data input
input 0 to 4327
(District 0)
Address Data input
input 0 to 4327
(District1)
RY/BY
After “15h” or “10h” Program command is input to device, physical programing starts as follows. For details
of Auto Program with Data Cache, refer to “Auto Page Program with Data Cache”.
District 0
District 1
Program
Selected
page
Reading & verification
The data is transferred (programmed) from the page buffer to the selected page on the rising edge of
/WE following input of the “15h” or “10h” command. After programming, the programmed data is
transferred back to the register to be automatically verified by the device. If the programming does not
succeed, the Program/Verify operation is repeated by the device until success is achieved or until the
maximum loop number set in the device is reached.
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2010-12-13C