TH58NVG5S0FTA20 Datasheet, PDF (32/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
Table 3. Command table (HEX)
Serial Data Input
Read
Column Address Change in Serial Data Output
Read with Data Cache
Read Start for Last Page in Read Cycle with Data Cache
Auto Page Program
Column Address Change in Serial Data Input
Auto Program with Data Cache
Multi Page Program
Read for Page Copy (2) with Data Out
Read for Copy-Back without Data Out
Copy-Back Program without Data Out
Auto Program with Data Cache during Page Copy (2)
Auto Program for last page during Page Copy (2)
Auto Block Erase
Page Program with 2KB Data
Copy-Back Program with 2KB Data
ID Read
Status Read
Status Read2 for Chip A or C
Status Read2 for Chip B or D
Status Read for Multi-Page Program or Multi Block Erase
Reset
First Set
80
00
05
31
3F
80
85
80
80
81
81
00
00
85
8C
8C
60
80 – 11
85 - 11
90
70
F1
F2
71
FF
Second Set
⎯
30
E0
⎯
⎯
10
⎯
15
11
15
10
3A
35
10
15
10
D0
80 - 10
85 - 10
⎯
⎯
⎯
⎯
⎯
⎯
HEX data bit assignment
(Example)
Serial Data Input: 80h
Acceptable while Busy
{
{
{
{
{
Table 4. Read mode operation states
CLE
Output select
L
Output Deselect
L
H: V_IH, L: V_IL
10000000
8 7 6 5 4 3 2 I/O1
ALE
CE
WE
RE
L
L
H
L
L
L
H
H
I/O1 to I/O8
Data output
High impedance
Power
Active
Active
32
2010-12-13C