TH58NVG5S0FTA20 Datasheet, PDF (37/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
(3) Notes
(a) Internal addressing in relation with the Districts
To use Multi Page Read operation, the internal addressing should be considered in relation with the District.
• The device contains four chips of NAND EEPROM.
• Each internal chip consists from 2 Districts.
• Each District consists from 2048 erase blocks.
• The allocation rule is follows.
(a) District 0: Block 0, Block 2, Block 4, Block 6,···, Block 4094
(b) District 1: Block 1, Block 3, Block 5, Block 7,···, Block 4095
(c) District 0: Block 4096, Block 4098, Block 4100, Block 4102,···, Block 8190
(d) District 1: Block 4097, Block 4099, Block 4101, Block 4103,···, Block 8191
Combination of (a) and (b) or (c) and (d) can only be selected.
(b) Address input restriction for the Multi Page Read operation
There are following restrictions in using Multi Page Read;
(Restriction)
District0 and District1 should be selected within the same chip.
Maximum one block should be selected from each District.
Same page address (PA0 to PA5) within two districts has to be selected.
For example;
(60) [District 0, Page Address 0x00000] (60) [District 1, Page Address 0x00040] (30)
(60) [District 0, Page Address 0x00001] (60) [District 1, Page Address 0x00041] (30)
(Acceptance)
There is no order limitation of the District for the address input.
For example, following operation is accepted;
(60) [District 0] (60) [District 1] (30)
(60) [District 1] (60) [District 0] (30)
It requires no mutual address relation between the selected blocks from each District.
(c) WP signal
Make sure WP is held to High level when Multi Page Read operation is performed
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2010-12-13C