TH58NVG5S0FTA20 Datasheet, PDF (3/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

BLOCK DIAGRAM
I/O1
to
I/O8
CE 1
CLE
ALE
WE
RE
WP
PSL
RY / BY 1
CE 2
TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
I/O
Control circuit
(Chip A, B)
Status register
Address register
Command register
Logic control
Control circuit
V_CC V_SS
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
RY / BY
I/O
Control circuit
HV generator
Status register
Address register
Command register
Logic control
Control circuit
Column buffer
Column decoder
Data register
Sense amp
Memory cell array
RY / BY 2
RY / BY
HV generator
(Chip C, D)
V_CC V_SS
3
2010-12-13C