TH58NVG5S0FTA20 Datasheet, PDF (47/73 Pages) Toshiba Semiconductor – 32 GBIT (4G × 8 BIT) CMOS NAND E2PROM

TOSHIBA CONFIDENTIAL TH58NVG5S0FTA20
B
RY / BY B
Command
10
input
8C
Address input
Data input
Address
CA0 to CA12, PA0 to PA18
(Page M+Rn)
10
11
70
Status output
t_PROG (*1)
Data Cache
10 ^{Data for Page M + Rn}
11 ^{Data for Page M + Rn}
Page Buffer
Page M + Rn − 1
Cell Array
Page N + Pn
10 Copy Page address (M + Rn) is input and if the data needs to be changed, changed data is input.
11 By issuing the 10h command, the data in the Page Buffer is programmed to Page M + Rn.
(*1) Since the last page programming by the 10h command is initiated after the previous cache program, the t_PROG here will be expected as the following,
t_PROG = t_PROG of the last page + tPROG of the previous page − ( command input cycle + address input cycle + data output/input cycle time of the last page)
NOTE) This operation needs to be executed within District-0 or District-1.
Data input is required only if previous data output needs to be altered.
If the data has to be changed, locate the desired address with the column and page address input after the 8Ch command, and change only the data that needs be changed.
If the data does not have to be changed, data input cycles are not required.
Make sure WP is held to High level when Page Copy (2) operation is performed.
Also make sure the Page Copy operation is terminated with 8Ch-10h command sequence
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2010-12-13C