DS92LV2421_16 Datasheet, PDF (9/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
Table 1. Pin Functions: DS92LV2422 (Deserializer) (continued)
NAME
PIN
NO.
TYPE ⁽¹⁾
DESCRIPTION ⁽²⁾
CHANNEL-LINK II — CML SERIAL INTERFACE
RIN+
49
I
True input, CML. The input must be AC-coupled with a 0.1-μF capacitor.
RIN-
50
I
Inverting input, CML. The input must be AC-coupled with a 0.1-μF capacitor.
CMF
Common-mode filter, analog.
51
I
VCM center-tap is a virtual ground which may be AC-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+
52
O
True output (receive signal after the equalizer), CML.
NC if not used or connect to test point for monitor. Requires I²C control to enable.
ROUT-
53
POWER AND GROUND⁽⁴⁾
O
Inverting output (receive signal after the equalizer), CML.
NC if not used or connect to test point for monitor. Requires I²C control to enable.
VDDL
29
P
Logic power, 1.8 V ± 5%
VDDIR
48
P
Input power, 1.8 V ± 5%
VDDR
43, 55
P
RX high-speed logic power, 1.8 V ± 5%
VDDSC
4, 58
P
SSCG power, 1.8 V ± 5%
VDDPR
57
P
PLL power, 1.8 V ± 5%
VDDCMLO
54
P
RX high-speed logic power, 1.8 V ± 5%
VDDIO
GND
13, 24, 38
DAP
P
LVCMOS I/O power, 1.8 V ± 5% or 3.3 V ± 10% (V_DDIO)
G
DAP is the large metal contact at the bottom side, located at the center of the WQFN
package. Connected to the ground plane (GND) with at least 9 vias.
(4) The V_DD (V_DDn and V_DDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms, then a capacitor on the
PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
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