DS92LV2421_16 Datasheet, PDF (31/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
Table 9. OSC_SEL (Oscillator) Configuration (continued)
OSC_SEL[2:0] INPUTS
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
H
L
H
L
L
H
H
H
L
L
H
L
H
H
H
L
H
H
H
CLKOUT OSCILLATOR FREQUENCY
50 MHz ± 40%
25 MHz ± 40%
16.7 MHz ± 40%
12.5 MHz ± 40%
10 MHz ± 40%
8.3 MHz ± 40%
6.3 MHz ± 40%
PDB
(DES)
RIN
(Diff.)
active serial stream
X
LOCK ^Z
DO[23:0], Z
CO1,CO2,CO3
CLKOUT* Z
(DES)
PASS
Z
L
L
L
f
L
H
L
L
f
H
L
H
Z
Z
Z
H
Z
OFF
Locking
Active
C0 or C1 Error
In Bit Stream
(Loss of LOCK)
CONDITIONS: * RFB = L, OSS_SEL = H , and OSC_SEL not equal to 000.
Active
OFF
Figure 29. Deserializer Outputs With Output State High and CLKOUT Oscillator Option Enabled
7.3.4.5 Deserializer OP_LOW (Optional)
The OP_LOW feature is used to hold the LVCMOS outputs (except for the LOCK output) at a low state. The user
must toggle the OP_LOW set / reset register bit to release the outputs to the normal toggling state.
NOTE
The release of the outputs can only occur when LOCK is high. When the OP_LOW feature
is enabled, anytime LOCK = low, the LVCMOS outputs toggle to a low state again. The
OP_LOW strap pin feature is assigned to output PASS pin 42.
Restrictions on other straps:
1. Other straps must not be used to keep the data and clock outputs at a true low state. Other features must be
selected through I²C.
2. The OSS_SEL function is not available when OP_LOW is enabled (tied high).
Outputs DO[23:0], CO[3:1], and CLKOUT are in TRI-STATE before PDB toggles high, because the OP_LOW
strap value has not been recognized until the DS92LV2422 powers up. Figure 30 shows the user controlled
release of OP_LOW and automatic reset of OP_LOW set on the falling edge of LOCK. Figure 31 shows the user
controlled release of OP_LOW and manual reset of OP_LOW set.
NOTE
Manual reset of OP_LOW can only occur when LOCK is high.
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