DS92LV2421_16 Datasheet, PDF (42/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Application Information (continued)
18-BIT RGB
B2
B3
B4
MSB B5
HS
VS
DE
GP0
GP1
GP2
GND
GND
GND
Scenario 3⁽¹⁾
Table 17. Alternate Color and Data Mapping (continued)
18-BIT RGB
G4
G5
GP4
GP5
B0
B1
B2
B3
B4
B5
HS
VS
DE
Scenario 2⁽²⁾
24-BIT RGB
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
Scenario 1⁽³⁾
2421 PIN
NAME
2422 PIN
NAME
DI14
DO14
DI15
DO15
DI16
DO16
DI17
DO17
DI18
DO18
DI19
DO19
DI20
DO20
DI21
DO21
DI22
DO22
DI23
DO23
CI1
CO1
CI2
CO2
CI3
CO3
2421 Pin Name 2422 Pin Name
24-BIT RGB
G6
G7
B0
B1
B2
B3
B4
B5
B6
B7
HS
VS
DE
Scenario 1⁽³⁾
18-BIT RGB
G4
G5
GP4
GP5
B0
B1
B2
B3
B4
B5
HS
VS
DE
Scenario 2⁽²⁾
18-BIT RGB
B2
B3
B4
MSB B5
HS
VS
DE
GP0
GP1
GP2
GND
GND
GND
Scenario 3⁽¹⁾
(1) Scenario 3 supports an 18-bit RGB color mapping, 3 un-embedded video control signals, and up to three general-purpose signals.
(2) Scenario 2 supports an 18-bit RGB color mapping, 3 embedded video control signals, and up to six general-purpose signals.
(3) Scenario 1 supports the 24-bit RGB color mapping, along with the 3 embedded video control signals. This is the native mode for the
chipset.
8.2 Typical Applications
8.2.1 DS92LV2421 Typical Connection
Figure 38 shows a typical application of the DS92LV2421 serializer in pin control mode for a 24-bit application.
The LVDS outputs require 100-nF AC-coupling capacitors to the line. The line driver includes internal
termination. Bypass capacitors are placed near the power supply pins. At a minimum, four 0.1-µF capacitors and
a 4.7-µF capacitor must be used for local device bypassing. System GPO (General Purpose Output) signals
control the PDB and BISTEN pins. In this application, the RFB pin is tied low to latch data on the falling edge of
the CLKIN. The application assumes connection to the companion deserializer (DS92LV2422), and therefore the
configuration pins CONFIG[1:0] are also both tied low. In this example, the cable is long, and therefore the
VODSEL pin is tied high and a De-Emphasis value is selected by the resistor R1. The interface to the host is
with 1.8-V LVCMOS levels, thus the VDDIO pin is connected also to the 1.8-V rail. The optional serial bus control
is not used in this example, thus the SCL, SDA, and ID[X] pins are left open. A delay cap is placed on the PDB
signal to delay the enabling of the device until power is stable.
42
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