DS92LV2421_16 Datasheet, PDF (44/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
8.2.1.2 Detailed Design Procedure
The DOUT± outputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are
placed near the power supply pins. A smaller capacitance capacitor must be located closer to the power supply
pins.
The VODSEL pin is tied to VDDIO for the long cable application. The de-emphasis pin may connect a resistor to
ground. Refer to Table 3. The PDB and BISTEN pins are assumed to be controlled by a microprocessor. The
PDB must remain in a low state until all power supply voltages reach the final voltage. The RFB pin is tied low to
latch data on the falling edge of the PCLK and tied high for the rising clock edge. The CONFIG[1:0] pins are set
depending on operating modes and backward compatibility. The SCL, SDA, and ID[X] pins are left open when
these serial bus control pins are unused. The RES[2:0] pins and DAP must be tied to ground.
8.2.1.3 Application Curve
Figure 39. Eye Diagram at CLK = 20 MHz
8.2.2 DS92LV2422 Typical Connection
Figure 40 shows a typical application of the DS92LV2422 deserializer in pin or strap control mode for a 24-bit
application. The LVDS inputs use 100-nF coupling capacitors to the line, and the receiver provides internal
termination. Bypass capacitors are placed near the power supply pins. At a minimum, seven 0.1-µF capacitors
and two 4.7-µF capacitors must be used for local device bypassing. System General Purpose Output (GPO)
signals control the PDB and the BISTEN pins. In this application, the RFB pin is tied low to strobe the data on the
falling edge of the CLKOUT.
Because the device is in pin or strap control mode, four 10-kΩ pullup resistors are used on the parallel output
bus to select the desired device features. CONFIG[1:0] is set to 01'b for normal mode with control signal filter
enabled, and this is accomplished with the strap pullup on DO23. The receiver input equalizer is also enabled
and set to provide 7.5 dB of gain, and this is accomplished with EQ[3:0] set to 1001'b with strap pullups on DO12
and DO15. To reduce parallel bus EMI, the SSCG feature is enabled and set to fmod = CLK/2168 and ±1% with
SSC[3:0] set to 0010'b and a strap pullup on DO4. The desired features are set with the use of the four pullup
resistors.
The interface to the target display is with 3.3-V LVCMOS levels, thus the VDDIO pin is connected to the 3.3-V
rail. The optional serial bus control is not used in this example, thus the SCL, SDA and ID[X] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling of the device until power is stable.
44
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422