DS92LV2421_16 Datasheet, PDF (46/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Table 19. Design Parameters
PARAMETER
VDDIO
VDDL, VDDSC, VDDPR, VDDR,
VDDIR, VDDCMLO
AC-Coupling Capacitor for DOUT±
EXAMPLE VALUE
1.8 V to 3.3 V
1.8 V
100 nF
8.2.2.2 Detailed Design Procedure
The RIN± inputs require 100-nF AC-coupling capacitors to the line. The power supply filter capacitors are placed
near the power supply pins. A smaller capacitance capacitor must be placed closer to the power supply pins.
The device has 22 control and configuration pins that are called strap pins. These pins include an internal
pulldown. For a high state, use a 10-kΩ resistor pullup to VDDIO.
The PDB and BISTEN pins are assumed to be controlled by a microprocessor. The PDB has to be in a low state
until all power supply voltages reach the final voltage. The SCL, SDA, and ID[X] pins are left open when these
serial bus control pins are unused.
The RES pin and DAP must be tied to ground.
8.2.2.3 Application Curves
Figure 41. Eye Diagram at CLK = 45 MHz
Figure 42. Eye Diagram at CLK = 65 MHz
9 Power Supply Recommendations
9.1 Power-Up Requirements and PDB Pin
The VDD (VDDn and VDDIO) supply ramp must be faster than 1.5 ms with a monotonic rise. If slower then 1.5
ms, then a capacitor on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the
recommended operating voltage. When PDB pin is pulled to VDDIO, TI recommends using a 10-kΩ pullup and a
22-µF capacitor to GND to delay the PDB input signal.
46
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422