DS92LV2421_16 Datasheet, PDF (2/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 4
6 Specifications....................................................... 10
6.1 Absolute Maximum Ratings .................................... 10
6.2 ESD Ratings............................................................ 10
6.3 Recommended Operating Conditions..................... 10
6.4 Thermal Information ................................................ 11
6.5 Electrical Characteristics – Serializer DC ............... 11
6.6 Electrical Characteristics – Deserializer DC ........... 12
6.7 Electrical Characteristics – DC and AC Serial Control
Bus ........................................................................... 13
6.8 Timing Requirements – DC and AC Serial Control
Bus ........................................................................... 13
6.9 Timing Requirements – Serializer for CLKIN.......... 13
6.10 Timing Requirements – Serial Control Bus........... 14
6.11 Switching Characteristics – Serializer................... 14
6.12 Switching Characteristics – Deserializer............... 15
6.13 Typical Characteristics .......................................... 21
7 Detailed Description ............................................ 22
7.1 Overview ................................................................. 22
7.2 Functional Block Diagrams ..................................... 22
7.3 Feature Description................................................. 23
7.4 Device Functional Modes........................................ 37
7.5 Register Maps ......................................................... 38
8 Application and Implementation ........................ 41
8.1 Application Information............................................ 41
8.2 Typical Applications ................................................ 42
9 Power Supply Recommendations...................... 46
9.1 Power-Up Requirements and PDB Pin ................... 46
10 Layout................................................................... 47
10.1 Layout Guidelines ................................................. 47
10.2 Layout Example .................................................... 49
11 Device and Documentation Support ................. 51
11.1 Device Support...................................................... 51
11.2 Documentation Support ........................................ 51
11.3 Related Links ........................................................ 51
11.4 Community Resource............................................ 51
11.5 Trademarks ........................................................... 51
11.6 Electrostatic Discharge Caution ............................ 51
11.7 Glossary ................................................................ 52
12 Mechanical, Packaging, and Orderable
Information ........................................................... 52
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2013) to Revision C
Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 1
• Updated thermal characteristic values based on latest simulation data ............................................................................. 11
• Changed deserializer LVCMOS DC and supply current specification test conditions based on latest production tests .... 12
• Changed I_OL test condition for V_OL at V_DDIO = 3.3 V to 3 mA ............................................................................................... 12
• Changed max value of Deserializer V_OL to 0.45 V .............................................................................................................. 12
• Changed test condition parameter for V_OL Serial Control Characteristic ............................................................................ 13
• Changed RPU = 10 kΩ condition for the Serial Control Bus Characteristics of t_R and t_F ................................................... 13
• Added notes for serializer and deserializer switching characteristics verified by characterization ...................................... 14
• Added corresponding pins for deserializer t_CLH and t_CHL parameter..................................................................................... 15
• Added test condition to t_DD deserializer parameter ............................................................................................................. 15
• Changed corrected units for deserializer lock time and delay parameter ........................................................................... 15
• Added serial stream and video control signal filter waveform to Feature Description ........................................................ 23
• Changed "NA" and "Disable" term in Table 5 and Table 6 to "Off" ..................................................................................... 28
• Changed output states to correct values based on OSS_SEL and PDB configuration in Table 7 ..................................... 29
• Added details for Deserializer Map Select strap pin configuration ...................................................................................... 33
• Added clarification on the state of deserializer outputs during BIST mode operation.......................................................... 33
• Added statement to set input to low when entering BIST mode with DS90C241 or DS90UR241 ..................................... 33
• Added note that ID[X] cannot be tied to VSS, as only four device addresses are supported ............................................. 35
• Added RID tolerance and tablenote that RID ≠ 0 Ω to set ID[X] ......................................................................................... 35
• Changed statement that CONFIG settings can also by programmed via register .............................................................. 37
2
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422