DS92LV2421_16 Datasheet, PDF (5/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
Pin Functions: DS92LV2421 (Serializer) (continued)
NAME
PIN
NO.
TYPE ⁽¹⁾
DESCRIPTION ⁽²⁾
Control signal input, LVCMOS with pulldown.
CI3
4
I
For display or video application: CI3 = Vertical sync input.
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed is
130 clock cycles wide.
CLKIN
10
I
Clock input, LVCMOS with pulldown.
Latch or data strobe edge set by RFB pin.
CONTROL AND CONFIGURATION
PDB
21
VODSEL
24
De-Emph
23
RFB
11
Power-down mode input, LVCMOS with pulldown.
PDB = 1, serializer is enabled (normal operation).
I
Refer to Power-Up Requirements and PDB Pin.
PDB = 0, serializer is powered down. When the serializer is in the power-down state, the
driver outputs (DOUT±) are both logic high, the PLL is shutdown, IDD is minimized. Control
Registers are RESET.
Differential driver output voltage select (this can also be control by I²C register access),
LVCMOS with pulldown.
I
VODSEL = 1, LVDS VOD is ±420 mV, 840 mV_p-p (typical) — long cable or de-emphasis
apps.
VODSEL = 0, LVDS VOD is ±280 mV, 560 mV_p-p (typical) — short cable (no de-emphasis),
low power mode.
De-emphasis control (this can also be controlled by I²C register access), analog with pullup.
I
De-emphasis = open (float) - disabled.
To enable de-emphasis, tie a resistor from this pin to GND or control through register (see
Table 3).
Clock input latch or data strobe edge select (this can also be controlled by I²C register
I
access), LVCMOS with pulldown.
RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
CONFIG[1:0]
13, 12
ID[X]
6
SCL
8
SDA
9
BISTEN
31
LVCMOS with pulldown.
00: Control Signal Filter DISABLED.
I
01: Control Signal Filter ENABLED.
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q-Q1.
11: Reverse compatibility mode to interface with the DS90C124.
I
I²C serial control bus device ID address select (optional), analog.
Resistor to Ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
I
I²C serial control bus clock input (optional), LVCMOS.
SCL requires an external pullup resistor to V_DDIO.
I/O
I²C serial control bus data input or output (optional), LVCMOS (open drain).
SDA requires an external pullup resistor V_DDIO.
BIST mode (optional), LVCMOS with pulldown.
I
BISTEN = 0, BIST is disabled (normal operation).
BISTEN = 1, BIST is enabled.
RES[2:0]
18, 16, 15
I
Reserved (tie low), LVCMOS with pulldown.
CHANNEL-LINK II – CML SERIAL INTERFACE
DOUT+
20
O
Noninverting output, CML.
The output must be AC-coupled with a 0.1-µF capacitor.
DOUT–
19
O
Inverting output, CML.
The output must be AC-coupled with a 0.1-µF capacitor.
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