DS92LV2421_16 Datasheet, PDF (34/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Step 3: To stop BIST mode, the deserializer BISTEN pin is set low. The deserializer stops checking the data, and
the final test result is held on the PASS pin. If the test ran error free, the PASS output is high. If there was one or
more errors detected, the PASS output is low. The PASS output state is held until a new BIST is run, the device
is RESET, or powered down. The BIST duration is user controlled by the duration of the BISTEN signal.
Step 4: To return the link to normal operation, the serializer BISTEN input is set low. The Link returns to normal
operation.
Figure 33 shows the waveform diagram of a typical BIST test for two cases. Case 1 is error-free, and Case 2
shows one with multiple errors. In most cases, it is difficult to generate errors due to the robustness of the link
(differential data transmission and so forth), thus they may be introduced by greatly extending the cable length,
faulting the interconnect, or reducing signal condition enhancements (de-emphasis, VODSEL, or Rx
equalization).
Normal
Step 1: SER in BIST
BIST
Wait
Step 2: Wait, DES in BIST
BIST
start
Step 3: DES in Normal
Mode - check PASS
BIST
stop
Step 4: SER in Normal
Figure 32. BIST Mode Flow Diagram
BISTEN
(SER)
BISTEN
(DES)
CLKOUT
(RFB = L)
DO[23:0]
CO1,CO2,CO3
DATA
(internal)
PASS
Prior Result
DATA
X
(internal)
PASS
Prior Result
X = bit error(s)
X
X
Normal
PRBS
BIST Test
BIST Duration
Figure 33. BIST Waveforms
PASS
FAIL
BIST
Result
Held
Normal
34
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