DS92LV2421_16 Datasheet, PDF (23/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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Functional Block Diagrams (continued)
DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
ROUT+
ROUT-
CMF
RIN+
RIN-
BISTEN
PDB
SCL
SCA
ID[x]
EQ
Timing and
Control
SSCG
DO[23:0]
CO1/DE
CO2/HS
CO3/VS
STRAP INPUT
LF_MODE
OS_CLKOUT
OS_DATA
OSS_SEL
RFB
EQ [3:0]
OSC_SEL [2:0]
SSC [3:0]
Error
Detector
Clock and
Data
Recovery
PASS
CLKOUT
LOCK
STRAP INPUT
OP_LOW
Copyright © 2016, Texas Instruments Incorporated
Figure 22. DS92LV2422 – Deserializer
7.3 Feature Description
7.3.1 Data Transfer
The DS92LV242x chipset transmits and receives a pixel of data in the following format: C1 and C0 represent the
embedded clock in the serial stream. C1 is always high and C0 is always low. The b[23:0] contains the
scrambled LVCMOS data. DCB is the DC-Balanced control bit. DCB is used to minimize the short and long-term
DC bias on the signal lines. This bit determines if the data is unmodified or inverted. DCA is used to validate data
integrity in the embedded data stream and can also contain encoded control (VS, HS, DE). Both DCA and DCB
coding schemes are generated by the serializer and decoded by the deserializer automatically. Figure 23
illustrates the serial stream per clock cycle.
NOTE
Figure 23 only illustrates the bits but does not actually represent the bit location as the bits
are scrambled and balanced continuously.
C
1
b
0
b
1
b
2
b
3
b
4
b
5
b
6
b
7
b
8
b
9
b
1
0
b
1
1
D
C
A
D
C
B
b
1
2
b
1
3
b
1
4
b
1
5
b
1
6
b
1
7
b
1
8
b
1
9
b
2
0
b
2
1
b
2
2
b
2
3
C
0
Figure 23. Channel Link II Serial Stream (DS92LV242x)
Copyright © 2010–2016, Texas Instruments Incorporated
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