DS92LV2421_16 Datasheet, PDF (22/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
7 Detailed Description
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7.1 Overview
The DS92LV242x chipset transmits and receives 24 bits of data and 3 control signals over a single serial CML
pair operating at 280 Mbps to 2.1 Gbps. The serial stream also contains an embedded clock, video control
signals, and the DC-balance information which enhances signal quality and supports AC coupling.
The deserializer can attain lock to a data stream without the use of a separate reference clock source, which
greatly simplifies system complexity and overall cost. The deserializer also synchronizes to the serializer
regardless of the data pattern, delivering true automatic plug and lock performance. It can lock to the incoming
serial stream without the need of special training patterns or sync characters. The deserializer recovers the clock
and data by extracting the embedded clock information, validating, and then deserializing the incoming data
stream, providing a parallel LVCMOS video bus to the display, ASIC, or FPGA.
The DS92LV242x chipset can operate in 24-bit color depth (with DE, HS, VS encoded within the serial data
stream). In 18-bit color applications, the three video control signals may be sent encoded within the serial bit
stream (restrictions apply, see Video Control Signal Filter – Serializer and Deserializer) along with six additional
general-purpose signals.
7.2 Functional Block Diagrams
VODSEL
De-Emph
DI[23:0]
CI1/DE
CI2/HS
CI3/VS
RFB
CLKIN
PDB
SCL
SCA
ID[x]
BISTEN
PLL
Pattern
Generator
Timing and
Control
DOUT+
DOUT-
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Figure 21. DS92LV2421 – Serializer
22
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