DS92LV2421_16 Datasheet, PDF (32/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
PDB
2.0V
LOCK
OP_ LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
User
controlled
ACTIVE
CLKOUT
TRI-
STATE
ACTIVE
Figure 30. OP_LOW Auto Set
ACTIVE
PDB
2.0V
LOCK
OP_LOW
SET
(Strap pin)
OP_ LOW
RELEASE/SET
(Register)
User
controlled
User
controlled
DO[23:0],
CO3, CO2, CO1
TRI-
STATE
ACTIVE
CLKOUT
TRI-
STATE
ACTIVE
Figure 31. OP_LOW Manual Set or Reset
7.3.4.6 Deserializer Clock Edge Select (RFB)
The RFB pin determines the edge that the data is strobed on. If RFB is high, output data is strobed on the rising
edge of CLKOUT. If RFB is low, data is strobed on the falling edge of CLKOUT. This allows for inter-operability
with downstream devices. The deserializer output does not need to use the same edge as the serializer input.
This feature may be controlled by the external pin or by register.
7.3.4.7 Deserializer Control Signal Filter (Optional)
The deserializer provides an optional control signal (C3, C2, C1) filter that monitors the three control signals and
eliminates any pulses or glitches that are 1 or 2 CLKOUT periods wide. Control signals must be 3 parallel clock
periods wide (in its high or low state, regardless of which state is active). This is set by the CONFIG[1:0] strap
option or by I²C register control.
32
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422