DS92LV2421_16 Datasheet, PDF (15/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
Switching Characteristics – Serializer (continued)
Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER
TEST CONDITIONS
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 75 MHz
t_DJIT
Serializer output total jitter
(see Figure 8)
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 43 MHz
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 10 MHz
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 75 MHz
λ_STXBW
Serializer jitter transfer
(function –3 dB bandwidth)
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 43 MHz
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 10 MHz
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 75 MHz
δ_STX
Serializer jitter transfer
(function peaking)
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 43 MHz
R_L = 100 Ω, de-emphasis = disabled, RANDOM
pattern, CLKIN = 10 MHz
MIN TYP MAX UNIT
0.28
0.27
UI ⁽⁴⁾
0.35
3.3
2.3
MHz
0.8
0.86
0.83
dB
0.28
(4) UI – Unit Interval is equivalent to one serialized data bit width (1 UI = 1 / [28 x CLK]). The UI scales with clock frequency.
6.12 Switching Characteristics – Deserializer
Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
t_RCP
CLK output period
t_RCP = t_TCP (CLKOUT)
SSCG = OFF, 10 to 75 MHz
13.3
40%
T
50%
t_RDC
CLK output duty cycle
CLKOUT
SSCG = ON, 10 to 20 MHz
SSCG = ON, 10 to 65 MHz
35%
40%
59%
53%
t_CLH
LVCMOS low-to-high transition DO[23:0], CO1,
time (see Figure 10)
CO2, CO3
V_DDIO = 1.8 V, C_L = 4 pF,
OS_CLKOUT/DATA = L
V_DDIO = 3.3 V, C_L = 4 pF,
OS_CLKOUT/DATA = H
2.1
2
t_CHL
LVCMOS high-to-low transition DO[23:0], CO1,
time (see Figure 10)
CO2, CO3
V_DDIO = 1.8 V, C_L = 4 pF,
OS_CLKOUT/DATA = L
V_DDIO = 3.3 V, C_L = 4 pF,
OS_CLKOUT/DATA = H
1.6
1.5
t_ROS
Data valid before CLKOUT,
setup time (see Figure 14)
V_DDIO = 1.71 to 1.89 V or 3 to 3.6 V, C_L = 4 pF
(lumped load), DO[23:0], CO1, CO2, CO3
0.23 × T 0.5 × T
t_ROH
t_DDLT
Data valid after CLKOUT, hold
time (see Figure 14)
Deserializer lock time
(see Figure 13)
V_DDIO = 1.71 to 1.89 V or 3 to 3.6 V, C_L = 4 pF
(lumped load), DO[23:0], CO1, CO2, CO3
CLKOUT = 10 MHz, SSC[3:0] = OFF⁽¹⁾
CLKOUT = 75 MHz, SSC[3:0] = OFF⁽¹⁾
CLKOUT = 10 MHz, SSC[3:0] = ON⁽¹⁾
CLKOUT = 65 MHz, SSC[3:0] = ON⁽¹⁾
0.33 × T 0.5 × T
3
4
30
6
t_DD
Deserializer delay, latency (see
Figure 11)
CLKOUT = 10 to 75 MHz, SSC[3:0] = OFF⁽²⁾
139 × T
MAX
100
60%
65%
60%
140 × T
UNIT
ns
ns
ns
ns
ns
ms
ns
(1) t_PLD and t_DDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an
active clock.
(2) Specification is verified by design and is not tested in production.
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