DS92LV2421_16 Datasheet, PDF (8/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Table 1. Pin Functions: DS92LV2422 (Deserializer) (continued)
NAME
PIN
NO.
TYPE ⁽¹⁾
OS_CLKOUT 11 [DO21]
I
OS_DATA
14 [DO19]
I
OP_LOW
42 [PASS]
I
OSS_SEL
17 [DO18]
I
RFB
18 [DO17]
I
EQ[3:0]
20 [DO15],
21 [DO14],
22 [DO13],
I
23 [DO12]
26 [DO10],
OSC_SEL[2:0] 27 [DO9],
I
28 [DO8]
34 [DO6],
SSC[3:0]
35 [DO5],
36 [DO4],
I
37 [DO3]
MAP_SEL[1:0]
40 [D],
41 [D]
I
CONTROL AND CONFIGURATION
PDB
59
I
ID[X]
SCL
SDA
BISTEN
RES
NC
56
I
3
I
2
I/O
44
I
47
I
1, 15, 16,
30, 31, 45,
—
46, 60
DESCRIPTION ⁽²⁾
Output CLKOUT slew select, STRAP or LVCMOS with pulldown.
OS_CLKOUT = 1, increased CLKOUT slew rate.
OS_CLKOUT = 0, normal CLKOUT slew rate (default).
This can also be controlled by I²C register access.
Output DO[23:0], CO1, CO2, CO3 slew select; STRAP or LVCMOS with pulldown.
OS_DATA = 1, Increased DO slew rate.
OS_DATA = 0, Normal DO slew rate (default).
This can also be controlled by I²C register access.
Outputs held low when LOCK = 1, STRAP or LVCMOS with pulldown.
NOTE: Do not use any other strap options with this strap function enabled.
OP_LOW = 1, all outputs are held low during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE (see Figure 30 and
Figure 31).
OP_LOW = 0, all outputs toggle normally as soon as LOCK goes high (default).
This can also be controlled by I²C register access.
Output sleep state select, STRAP or LVCMOS with pulldown.
OSS_SEL is used in conjunction with PDB to determine the state of the outputs in power
down (see Table 7).
NOTE: OSS_SEL strap cannot be used if OP_LOW = 1.
This can also be controlled by I²C register access.
Clock output strobe edge select, STRAP or LVCMOS with pulldown.
RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I²C register access.
Receiver input equalization, STRAP or LVCMOS with pulldown (see Table 4).
This can also be controlled by I²C register access.
Oscillator select, STRAP or LVCMOS with pulldown (see Table 8 and Table 9).
This can also be controlled by I²C register access.
Spread spectrum clock generation (SSCG) range select, STRAP or LVCMOS with pulldown
(see Table 5 and Table 6).
This can also be controlled by I²C register access.
Bit mapping reverse compatibility or DS90UR241 options, STRAP or LVCMOS with pulldown.
Pin or register control. Default setting is 00'b (see Table 10).
Power-down mode input, LVCMOS with pulldown.
PDB = 1, deserializer is enabled (normal operation). Refer to Power-Up Requirements and
PDB Pin.
PDB = 0, deserializer is in power down.
When the deserializer is in the power-down state, the LVCMOS output state is determined by
Table 7. Control registers are RESET.
I²C serial control bus device ID Address Select (optional), analog.
Resistor to ground and 10-kΩ pullup to 1.8-V rail (see Table 11).
I²C serial control bus clock input (optional), LVCMOS.
SCL requires an external pullup resistor to V_DDIO.
I²C serial control bus data input or output (optional), LVCMOS open drain.
SDA requires an external pullup resistor to V_DDIO.
BIST enable input (optional), LVCMOS with pulldown.
BISTEN = 0, BIST is disabled (normal operation).
BISTEN = 1, BIST is enabled.
Reserved (tie low), LVCMOS with pulldown.
Not connected, leave pin open (float).
8
Submit Documentation Feedback
Copyright © 2010–2016, Texas Instruments Incorporated
Product Folder Links: DS92LV2421 DS92LV2422