DS92LV2421_16 Datasheet, PDF (14/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
6.10 Timing Requirements – Serial Control Bus
Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER
TEST CONDITIONS
f_SCL
SCL clock frequency
Standard mode
Fast mode
t_LOW
SCL low period
Standard mode
Fast mode
t_HIGH
SCL high period
Standard mode
Fast mode
t_HD;STA
Hold time for a start or a repeated start ^{Standard mode}
condition (see Figure 18)
Fast mode
t_SU:STA
Set up time for a start or a repeated
start condition (see Figure 18)
Standard mode
Fast mode
t_HD;DAT
Data hold time
(see Figure 18)
Standard mode
Fast mode
t_SU;DAT
Data set up time
(see Figure 18)
Standard mode
Fast mode
t_SU;STO
Set up time for STOP condition
(see Figure 18)
Standard mode
Fast mode
t_BUF
Bus free time (between STOP and
START; see Figure 18)
Standard mode
Fast mode
t_r
SCL and SDA rise time
(see Figure 18)
Standard mode
Fast mode
t_f
SCL and SDA fall time
(see Figure 18)
Standard mode
Fast mode
6.11 Switching Characteristics – Serializer
Over recommended operating supply and temperature ranges (unless otherwise noted).
PARAMETER
TEST CONDITIONS
t_LHT
Serializer output low-to-high
transition time (see Figure 3)
R_L = 100 Ω, de-emphasis = disabled, VODSEL = 0
R_L = 100 Ω, de-emphasis = disabled, VODSEL = 1
t_HLT
Serializer output high-to-low
transition time (see Figure 3)
R_L = 100 Ω, de-emphasis = disabled, VODSEL = 0
R_L = 100 Ω, de-emphasis = disabled, VODSEL = 1
t_DIS
Input data, setup time
(see Figure 4)
DI[23:0], CI1, CI2, CI3 to CLKIN
t_DIH
Input data, hold time
(see Figure 4)
CLKIN to DI[23:0], CI1, CI2, CI3
t_XZD
Serializer output active to OFF
delay (see Figure 6)⁽¹⁾
t_PLD
Serializer PLL lock time
(see Figure 5)^(1)(2)(3)
R_L = 100 Ω
t_SD
Serializer delay, latency
(see Figure 7)⁽¹⁾
R_L = 100 Ω
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MIN NOM MAX UNIT
100
kHz
400
4.7
μs
1.3
4
μs
0.6
4
μs
0.6
4.7
μs
0.6
0
3.45
μs
0
0.9
250
ns
100
4
μs
0.6
4.7
μs
1.3
1000
ns
300
300
ns
300
MIN TYP MAX UNIT
200
ps
200
200
ps
200
2
ns
2
ns
8
15 ns
1.4
10 ms
144 × T 145 × T ns
(1) Specification is verified by characterization and is not tested in production.
(2) t_PLD and t_DDLT is the time required by the serializer and deserializer, respectively, to obtain lock when exiting power-down state with an
active clock.
(3) When the serializer output is at TRI-STATE the Deserializer loses PLL lock. Resynchronization and Re-lock must occur before data
transfer require t_PLD
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