DS92LV2421_16 Datasheet, PDF (26/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
7.3.3.3 Power-Saving Features
7.3.3.3.1 Serializer Power-Down Feature (PDB)
The serializer has a PDB input pin to enable or power down the device. This pin is controlled by the host and is
used to save power, disabling the link when it is not needed. In power-down mode, the high-speed driver outputs
are both pulled to VDD and present a 0-V VOD state.
NOTE
In power down, the optional serial bus control registers are RESET.
7.3.3.3.2 Serializer Stop Clock Feature
The serializer enters a low power SLEEP state when the CLKIN is stopped. A STOP condition is detected when
the input clock frequency is less than 3 MHz. The clock must be held at a static low or high state. When the
CLKIN starts again, the serializer locks to the valid input clock and then transmits the serial data to the
deserializer.
NOTE
In STOP CLOCK SLEEP, the optional serial bus control register values are RETAINED.
7.3.3.3.3 1.8-V or 3.3-V VDDIO Operation
The serializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (V_DDIO) for host
compatibility. The 1.8-V levels offer lower noise (EMI) and also system power savings.
7.3.3.3.4 Deserializer Power-Down Feature (PDB)
The deserializer has a PDB input pin to enable or power down the device. This pin can be controlled by the
system to save power, disabling the deserializer when the display is not needed. An auto-detect mode is also
available. In this mode, the PDB pin is tied high and the deserializer enters power down when the serial stream
stops. When the serial stream starts up again, the deserializer locks to the input stream and assert the LOCK pin
and output valid data. In power-down mode, the data and CLKOUT output states are determined by the
OSS_SEL status.
NOTE
In power down, the optional serial bus control registers are RESET.
7.3.3.3.5 Deserializer Stop Stream SLEEP Feature
The deserializer enters a low power SLEEP state when the input serial stream is stopped. A STOP condition is
detected when the embedded clock bits are not present. When the serial stream starts again, the deserializer
then locks to the incoming signal and recover the data.
NOTE
In STOP STREAM SLEEP, the optional serial bus control registers values are RETAINED.
7.3.3.4 Serializer Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on. If RFB is high, input data is latched on the rising
edge of the CLKIN. If RFB is low, input data is latched on the falling edge of the CLKIN. Serializer and
deserializer may be set differently. This feature may be controlled by the external pin or by register.
7.3.3.5 Optional Serial Bus Control
See Optional Serial Bus Control.
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