DS92LV2421_16 Datasheet, PDF (29/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
Table 6. SSCG Configuration (LF_MODE = H) – Deserializer Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] INPUTS
LF_MODE = H (10 - 20 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
RESULT
fdev (%)
Off
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
fmod (kHz)
Off
CLK/620
CLK/370
CLK/258
CLK/192
7.3.4.2.4 1.8-V or 3.3-V VDDIO Operation
The deserializer parallel bus and serial bus interface can operate with 1.8-V or 3.3-V levels (V_DDIO) for target
(display) compatibility. The 1.8-V levels offer a lower noise (EMI) and also system power savings.
7.3.4.3 Deserializer Clock-Data Recovery Status Flag (LOCK) And Output State Select (OSS_SEL)
When PDB is driven high, the CDR PLL begins locking to the serial input and LOCK goes from TRI-STATE to
low (depending on the value of the OSS_SEL setting). After the DS92LV2422 completes its lock sequence to the
input serial data, the LOCK output is driven high, indicating valid data and clock recovered from the serial input is
available on the parallel bus and clock outputs. The CLKOUT output is held at its current state at the change
from OSC_CLK (if this is enabled through OSC_SEL) to the recovered clock (or vice versa).
If there is a loss of clock from the input serial stream, LOCK is driven low and the state of the outputs are based
on the OSS_SEL setting (strap pin configuration or register).
7.3.4.4 Deserializer Oscillator Output (Optional)
The deserializer provides an optional clock output when the input clock (serial stream) has been lost. This is
based on an internal oscillator. The frequency of the oscillator may be selected. This feature may be controlled
by the external pin or by register (see Table 8 and Table 9).
Table 7. OSS_SEL and PDB Configuration (Deserializer Outputs)
SERIAL
INPUT
X
X
Static
Static
Active
INPUTS
PDB
L
L
H
H
H
OSS_SEL
L
H
L
H
X
CLKOUT
Z
Z
L
Z
Active
OUTPUTS
DO[23:0],
CO1, CO2,
CO3
LOCK
Z
Z
Z
Z
L
L
Z ⁽¹⁾
L
Active
H
PASS
Z
Z
L
L
H
(1) If DO[23:0], CO[3:1] pin is strapped high, the output is pulled up.
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