DS92LV2421_16 Datasheet, PDF (36/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
Table 12. ID[X] Resistor Value – DS92LV2422 Deserializer
RESISTOR
RID kΩ⁽¹⁾
(5% TOL)
0.47
2.7
8.2
Open
ADDRESS
7'b
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
ADDRESS
8'b
0 APPENDED (WRITE)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
(1) RID ≠ 0 Ω. Do not connect directly to VSS (GND). This is not a valid address.
The serial bus protocol is controlled by START, START-repeated, and STOP phases. A START occurs when
SCL transitions low while SDA is high. A STOP occurs when SDA transition high while SCL is also high (see
Figure 35).
SDA
SCL
S
START condition, or
START repeat condition
P
STOP condition
Figure 35. START and STOP Conditions
To communicate with a remote device, the host controller (master) sends the slave address and listens for a
response from the slave. This response is referred to as an acknowledge bit (ACK). If a slave on the bus is
addressed correctly, it Acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't
match the slave address of a device, it Not-acknowledges (NACKs) the master by letting SDA be pulled high.
ACKs also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the master is reading data, the master ACKs after every
data byte is received to let the slave know it wants to receive another data byte. When the master wants to stop
reading, it NACKs after the last data byte and creates a stop condition on the bus. All communication on the bus
begins with either a start condition or a repeated start condition. All communication on the bus ends with a stop
condition. A READ is shown in Figure 36 and a WRITE is shown in Figure 37.
NOTE
During initial power-up, a delay of 10 ms is required before the I²C will respond.
If the serial bus is not required, the three pins may be left open (NC).
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
S
Slave Address
a
A
2
A
1
A
0
1
c
k
Data
a
c
k
P
Figure 36. Serial Control Bus — READ
Slave Address
Register Address
S
A
2
A
1
A
0
a
0
c
k
a
c
k
Data
a
c
k
P
Figure 37. Serial Control Bus — WRITE
36
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