DS92LV2421_16 Datasheet, PDF (27/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
7.3.3.6 Optional BIST Mode
See Built-In Self Test (BIST).
7.3.4 Deserializer Functional Description
The deserializer converts a single input serial data stream to a wide parallel output bus and also provides a
signal check for the chipset Built-In Self Test (BIST) mode. The device can be configured through external pins
and strap pins or through the optional serial control bus. The deserializer features enhance signal quality on the
link by supporting an equalizer input and Channel Link II data coding that provides randomization, scrambling,
and DC balancing of the data. The deserializer includes multiple features to reduce EMI associated with display
data transmission. This includes the randomization and scrambling of the data and output spread spectrum clock
generation (SSCG) support. The deserializer features power-saving features with a power-down mode and
optional LVCMOS (1.8 V) interface compatibility.
7.3.4.1 Signal Quality Enhancers
7.3.4.1.1 Deserializer Input Equalizer Gain (EQ)
The deserializer can enable receiver input equalization of the serial stream to increase the eye opening to the
deserializer input.
NOTE
This function cannot be seen at the RxIN± input but can be observed at the serial test port
(ROUT±) enabled through the serial bus control registers. The equalization feature may be
controlled by the external pin or by register.
Table 4. Receiver Equalization Configuration Table
EQ3
L
L
L
L
H
H
H
H
X
EQ2
L
L
H
H
L
L
H
H
X
INPUTS
EQ1
L
H
L
H
L
H
L
H
X
EQ0
H
H
H
H
H
H
H
H
L
(1) Default Setting is EQ = Off
7.3.4.2 EMI Reduction Features
EFFECT
≈1.5 dB
≈3 dB
≈4.5 dB
≈6 dB
≈7.5 dB
≈9 dB
≈10.5 dB
≈12 dB
OFF ⁽¹⁾
7.3.4.2.1 Deserializer Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel bus outputs (DO[23:0], CO[3:1], and CLKOUT) of the deserializer feature a selectable output slew.
The DATA (DO[23:0], CO[3:1]) are controlled by strap pin or register bit OS_DATA. The CLKOUT is controlled by
strap pin or register bit OS_CLKOUT. When the OS_CLKOUT/DATA = H, the maximum slew rate is selected.
When the OS_PCLK/DATA = L, the minimum slew rate is selected. Use the higher slew rate setting when driving
longer traces or a heavier capacitive load.
7.3.4.2.2 Deserializer Common-Mode Filter Pin (CMF) (Optional)
The deserializer provides access to the center tap of the internal termination. A capacitor may be placed on this
pin for additional common-mode filtering of the differential pair. This can be useful in high-noise environments for
additional noise rejection capability. A 4.7-µF capacitor may be connected from this pin to Ground.
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