DS92LV2421_16 Datasheet, PDF (28/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
www.ti.com
7.3.4.2.3 Deserializer SSCG Generation (Optional)
The deserializer provides an internally generated spread spectrum clock (SSCG) to modulate its outputs. Both
clock and data outputs are modulated. This aids to lower system EMI. Output SSCG deviations of ±2% (4% total)
at up to 100-kHz modulations are available (see Table 5). This feature may be controlled by external strap pins
or by register.
NOTE
The device supports SSCG function with CLKOUT = 10 MHz to 65 MHz. When the
CLKOUT = 65 MHz to 75 MHz, it is required to disable the SSCG function (SSC[3:0] =
0000).
Frequency
F_CLKOUT+
F_CLKOUT
F_CLKOUT-
fdev(max)
1/fmod
Figure 26. SSCG Waveform
fdev(min)
Time
Table 5. SSCG Configuration (LF_MODE = L) – Deserializer Output
SSC3
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
SSC[3:0] INPUTS
LF_MODE = L (20 - 65 MHz)
SSC2
SSC1
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
L
L
L
L
L
H
L
H
H
L
H
L
H
H
H
H
SSC0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
RESULT
fdev (%)
Off
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
±2
±0.5
±1
±1.5
fmod (kHz)
Off
CLK/2168
CLK/1300
CLK/868
CLK/650
28
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