DS92LV2421_16 Datasheet, PDF (47/59 Pages) Texas Instruments – 10-MHz to 75-MHz, 24-Bit Channel Link II Serializer And Deserializer

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10 Layout
DS92LV2421, DS92LV2422
SNLS321C – MAY 2010 – REVISED MAY 2016
10.1 Layout Guidelines
Circuit board layout and stack-up for the LVDS serializer and deserializer devices must be designed to provide
low-noise power feed to the device. Good layout practice also separates high frequency or high-level inputs and
outputs to minimize unwanted stray noise pickup, feedback, and interference. Power system performance may
be greatly improved by using thin dielectrics (2 to 4 mils) for power or ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with low-inductance parasitics, which has proven
especially effective at high frequencies and makes the value and placement of external bypass capacitors less
critical. External bypass capacitors must include both RF ceramic and tantalum electrolytic types. RF capacitors
may use values in the range of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2 µF to 10 µF range.
Voltage rating of the tantalum capacitors must be at least 5x the power supply voltage being used.
Surface-mount capacitors are recommended due to their smaller parasitics. When using multiple capacitors per
supply pin, place the smaller value closer to the pin. A large bulk capacitor is recommend at the point of power
entry. This is typically in the 50 µF to 100 µF range and smooths low frequency switching noise. TI recommends
connecting power and ground pins directly to the power and ground planes with bypass capacitors connected to
the plane, with vias on both ends of the capacitor. Connecting power or ground pins to an external bypass
capacitor increases the inductance of the path.
A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body size
reduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency of
these external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiple
capacitors are often used to achieve low impedance between the supply rails over the frequency of interest. At
high frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducing
the impedance at high frequency.
Some devices provide separate power and ground pins for different portions of the circuit. This is done to isolate
switching noise effects between different sections of the circuit. Separate planes on the PCB are typically not
required. Pin description tables typically provide guidance on which circuit blocks are connected to which power
pin pairs. In some cases, an external filter may be used to provide clean power to sensitive circuits such as
PLLs.
Use at least a four-layer board with a power and ground plane. Place LVCMOS signals away from the CML lines
to prevent coupling from the LVCMOS lines to the CML lines. Closely-coupled differential lines of 100 Ω are
typically recommended for LVDS interconnects. The closely coupled lines help to ensure that coupled noise
appears as common mode and thus is rejected by the receivers. The tightly coupled lines also radiate less.
10.1.1 WQFN (LLP) Stencil Guidelines
Stencil parameters such as aperture area ratio and the fabrication process have a significant impact on paste
deposition. Inspection of the stencil prior to placement of the LLP (WQFN) package is highly recommended to
improve board assembly yields. If the via and aperture openings are not carefully monitored, the solder may flow
unevenly through the DAP. Stencil parameters for aperture opening and via locations are shown below:
Figure 43. No Pullback LLP, Single Row Reference Diagram
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